Conventional memory devices, such as standard static random access memories (SRAMs), including both synchronous and asynchronous types, can provide the fast performance needed for many applications. However, other applications can have a need for even higher data throughput rates. As but one example, in many network hardware devices there is a need for memory devices having an even higher data throughput rate.
One type of memory device developed to meet high throughput applications is the Quad Data Rate™ or QDR™ SRAM (such as those manufactured by Cypress Semiconductor Corporation, of San Jose, Calif.). To better understand various features of the embodiments of the present invention, examples of QDR™ SRAMs will now be described.
A block diagram of one example of a QDR™ SRAM is set forth in FIG. 8, and designated by the general reference character 800. As shown in FIG. 8, a QDR™ SRAM can receive write data D via one port and output read data Q via another port. Further, such data can be read or written at a “double” data rate. Thus, four data operations (e.g., two reads and two writes) can occur in a single clock cycle.
Referring still to FIG. 8, addresses (A) and write data (D) can be latched on both rising and falling edges of a clock signal (CLK and its complement CLK#). An active low read pulse RPS# can indicate a read operation, while an active low write pulse WPS# can indicate a write operation. Read data (Q) can be output in synchronism with an “echo” clock (CQ and its complement CQ#). An echo clock (CQ) may be synchronous with another clock signal (not shown), or can be synchronous with clock signal CLK in a “single” clock mode of operation.
A more detailed example of a QDR™ SRAM is shown in FIGS. 9A and 9B. FIG. 9A is a block schematic diagram designating the QDR™ SRAM by the general reference character 900. The QDR™ SRAM 900 includes a memory cell array 902 with two sections (904-a and 904-b). The memory cell array 902 can be accessed in a write operation according to a write address decoder 906 and in a read operation according to a read address decoder 908.
In a write operation, write data D[7:0] can be applied to memory cell array 902 by way of a write register, that includes write registers 910-a and 910-b for writing data to sections (904-a and 904-b), respectively. Write data D[7:0] can be received on a write bus 912. A write address A[19:0] received on address bus 914 can be latched in a write address register 916 and applied to write address decoder 906.
In a read operation, a read address A[19:0] received on address bus 914 can be latched in a read address register 918 and applied to read address decoder 908. Read data Q[7:0] can be output by way of a read register 920 through data registers 922-a to 922-c onto read data bus 924.
Timing of operations within QDR™ SRAM 900 can be controlled according to clock generator 926. Clock generator 926 can receive a clock signal K and its complement K#. Further, control signals for such operations can be generated by control circuits 928 and 930. As shown in FIG. 9A, control circuit 928 can receive a reference voltage Vref, which can be used to distinguish a logic high from a logic low, a write pulse WPS#, and byte write select signals BWS#[1:0]. Control circuit 930 can receive a read pulse RPS#, and optionally, an output clock signal C and its complement C#.
FIG. 9B is a timing diagram showing the operation of the QDR™ SRAM of FIG. 9A.
Referring now to FIG. 9B in conjunction with FIG. 9A, at time t0, clock signal K can transition high. At this time both a write pulse WPS# (which is active low) and a read pulse RPS# (which is also active low) can be low. In response to such control signals QDR™ SRAM 900 can latch a read address (A0) present on address bus 914 on the rising edge of clock signal K. In addition, the QDR™ SRAM 900 can prepare to latch a write address on the next falling edge of clock signal K (or rising edge of complementary clock signal K#). At the same time, a first write data value (D10) on write data bus 912 can be latched within write address register 910-a. 
At time t1, clock signal K can transition low (while complementary clock signal K# transitions high). Because write pulse WPS# was low at time t0, QDR™ SRAM 900 can latch a write address (A1) present on address bus 914 on the falling edge of clock signal K. At this time, a second write data value (D11) on write data bus 912 can be latched within write address register 910-b. 
In a similar fashion to times t0 and t1, at times t3 and t4 another read address A2 and another write address A3 can be latched, respectively. Further, at times t4 and t5 a third read address A4 and write address (the same address A4) can be latched.
As illustrated by the single clock signal cycle between times t3 and t5, as write data D40 and D41 are being input, read data Q00 and Q01 (corresponding to read address A0) can be output. Hence a “quadruple” data throughput rate can be achieved.
While QDR™ SRAMs and similar memory devices can provide a high data throughput speed for memory access intensive applications, such as network search engines and the like, there is always a need for even higher throughput devices in order to improve the performance of such systems even further.
In light of the above, it would be desirable to arrive at some way of increasing that data throughput of a memory device beyond that of conventional QDR™ SRAMs and similar memory devices.